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MM908E626 Rev 3.0, 12/2005
Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication
The 908E626 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOS TM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator (ICG) module. The analog control die provides fully protected H-Bridge outputs, voltage regulator, autonomous watchdog, and local interconnect network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive stepper applications like climate control and light-levelling. Features * High-Performance M68HC08EY16 Core * 16 K Bytes of On-Chip Flash Memory * 512 Bytes of RAM * Internal Clock Generation Module * Two 16-Bit, 2-Channel Timers * 10-Bit Analog-to-Digital Converter * Four Low RDS(ON) Half-Bridge Outputs * 13 Microcontroller I/Os
908E626
STEPPER MOTOR DRIVER WITH EMBEDDED MCU AND LIN
DWB SUFFIX 98ARL105910 54-TERMINAL SOICWB-EP
Device MM908E626AVDWB
Temperature Range (TA) -40C to 115C
Package 54 SOIC WB-EP
908E626 Simplified Application Diagram 908E626
LIN VREFH VDDA EVDD VDD VREFL VSSA EVSS VSS RST RST_A IRQ IRQ_A SS PTB1/AD1 RXD PTE1/RXD PTD1/TACH1 FGEN BEMF PTD0/TACH0/BEMF VSUP[1:3]
HB1 HB2 HB3 HB4 S N Bipolar Step Motor
HVDD
Switchable Internal VDD Output
GND[1:2] EP
Port A I/Os Port B I/Os Port C I/Os
Microcontroller Ports
Figure 1. 908E626 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
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PTD0/TACH0 PTB1/AD1 VSUP1-3 BEMF GND1-2 RST_A IRQ_A FGEN PTD1/TACH1 PTE1/RXD VREFH SS EVDD VREFL VDDA
M68HC08 CPU CPU ALU Registers
908E626
EVSS RXD RST LIN IRQ Single Breakpoint Break Module 5-Bit Keyboard Interrupt Module PTE0/TXD TXD LIN Physical Layer Switched VDD Driver & Diagnostic 2-channel Timer Interface Module A 2-channel Timer Interface Module B Enhanced Serial Communication Interface Module Computer Operating Properly Module PTC0/MISO PTC1/MOSI PTA5/SPSCK MOSI SPSCK BEMF FGEN Half Bridge Driver & Diagnostic Autonomous Watchdog Chip Temp VSUP Prescaler BEMF BEMF FGEN Half Bridge Driver & Diagnostic VSUP HB4 MISO BEMF SPI & CONTROL FGEN Half Bridge Driver & Diagnostic VSUP HB3 Serial Peripheral Interface Module Configuration Register Module Periodic Wake-up Timebase Module Arbiter Module Prescaler Module BEMF Module SS Interrupt Control Module FGEN Half Bridge Driver & Diagnostic VSUP HB2 VSUP HB1 Reset Control Module Voltage Regulator VSSA VSS VDD HVDD Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes Flash programming (Burn-in), 1024 Bytes User Flash Vector Space, 36 Bytes OSC2 Internal Clock OSC1 Generator Module RST IRQ Single External IRQ Module 24 Integral System Integration Module Internal Bus VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS Power-ON Reset Module Security Module PORT C DDRC DDRA PORT A PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTB0/AD0 PTD0/TACH0 PTE1/RXD PTE0/TXD Analog Die ADOUT Analog Multiplexer PORT D PORT E DDRD DDRE DDRB PORT B PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB0/AD0 MCU Die PTB0/AD0
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTB3/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6/TBCH0
PTB7/AD7/TBCH1
Figure 2. Figure 1. 908E626 Simplified Internal Block Diagram
PTC2/MCLK
PTC3/OSC2
PTC4/OSC1
Analog Integrated Circuit Device Data Freescale Semiconductor
FLSVPP
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
Transparent Top View of Package
PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3
IRQ RST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42
PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF
RST_A IRQ_A SS
Exposed Pad
41 40 39 38 37 36 35 34 33 32 31 30 29 28
LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2
PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS NC VDD NC NC NC HVDD NC HB4 VSUP3 GND2 HB3 NC
Figure 3. 908E626 Terminal Connections Table 1. 908E626 TERMINAL DEFINITIONS A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Die MCU Terminal 1 2 6 7 8 11 3 4 5 9 10 12 13 14, 21, 22, 28, 33, 35, 36, 37, 39 Terminal Name PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK IRQ RST PTD0/TACH0/BEMF PTD1/TACH1 NC Formal Name Port B I/Os Definition These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU.
MCU
Port C I/Os
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. This terminal is an asynchronous external interrupt input terminal. This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. These terminals are special-function, bidirectional I /O port terminals that are shared with other functional modules in the MCU. Not connected.
MCU MCU MCU -
External Interrupt Input External Reset Port D I /Os No Connect
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TERMINAL CONNECTIONS
Table 1. 908E626 TERMINAL DEFINITIONS A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Die MCU MCU MCU MCU MCU Terminal 42 43 48 44 47 45 46 49 50 52 53 54 51 15 16 17 18 19 20 23 26 29 32 24 27 31 25 30 34 Terminal Name PTE1/ RXD VREFL VREFH VSSA VDDA EVSS EVDD PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 FLSVPP FGEN BEMF
RST_A IRQ_A
Formal Name Port E I /O ADC References ADC Supply Terminals MCU Power Supply Terminals Port A I /Os
Definition This terminal is a special-function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU. These terminals are the reference voltage terminals for the analogto-digital converter (ADC). These terminals are the power supply terminals for the analog-todigital converter. These terminals are the ground and power supply terminals, respectively. The MCU operates from a single power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU.
MCU Analog Analog Analog Analog Analog Analog Analog
Test Terminal Current Limitation Frequency Input Back Electromagnetic Force Output Internal Reset Internal Interrupt Output Slave Select LIN Bus Half-Bridge Outputs
For test purposes only. Do not connect in the application. This is the input terminal for the half-bridge current limitation PWM frequency. This terminal gives the user information about back electromagnetic force (BEMF). This terminal is the bidirectional reset terminal of the analog die. This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal is the SPI slave select terminal for the analog chip. This terminal represents the single-wire bus transmitter and receiver. This device includes power MOSFETs configured as four half-bridge driver outputs. These outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. These terminals are device power supply terminals.
SS
LIN HB1 HB2 HB3 HB4 VSUP1 VSUP2 VSUP3 GND1 GND2 HVDD
Analog
Power Supply Terminals Power Ground Terminals Switchable VDD Output Voltage Regulator Output Voltage Regulator Ground LIN Transceiver Output Exposed Pad
Analog Analog
These terminals are device power ground connections. This terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors. The + 5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. Ground terminal for the connection of all non-power ground connections (microcontroller and sensors). This terminal is the output of LIN transceiver. The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board.
Analog Analog Analog -
38 40 41 EP
VDD VSS RXD Exposed Pad
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Analog Integrated Circuit Device Data Freescale Semiconductor
MAXIMUM RATINGS
MAXIMUM RATINGS
MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device.
Rating Symbol Value Unit
ELECTRICAL RATINGS
Supply Voltage Analog Chip Supply Voltage under Normal Operation (SteadyState) Analog Chip Supply Voltage under Transient Conditions Microcontroller Chip Supply Voltage Input Terminal Voltage Analog Chip Microcontroller Chip Maximum Microcontroller Current per Terminal All Terminals Except VDD, VSS, PTA0 : PTA6, PTC0 : PTC1 Terminals PTA0 : PTA6, PTC0 : PTC1 Maximum Microcontroller VSS Output Current Maximum Microcontroller VDD Input Current LIN Supply Voltage Normal Operation (Steady-State) Transient Conditions (1) ESD Voltage Human Body Model (2) Machine Model (3) Charge Device Model (4) VESD1 VESD2 VESD3 3000 150 500 VBUS(SS) VBUS(DYNAMIC) -18 to 28 40 V IPIN(1) IPIN(2) IMVSS IMVDD 15 25 100 100 mA mA V VIN (ANALOG) VIN (MCU) - 0.3 to 5.5 VSS - 0.3 to VDD + 0.3 mA V
(1)
V VSUP(SS) VSUP(PK) VDD - 0.3 to 28 - 0.3 to 40 - 0.3 to 6.0
THERMAL RATINGS
Storage Temperature Operating Case Temperature (5) Operating Junction Temperature(6) Peak Package Reflow Temperature During Solder Mounting (7) TSTG TC TJ TSOLDER - 40 to 150 - 40 to 115 - 40 to 135 245 C C C C
Notes 1. Transient capability for pulses with a time of t < 0.5 sec. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 3. 4. 5. 6. 7. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). ESD3 testing is performed in accordance with Charge Device Model, robotic (CZAP = 4.0 pF). The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation on the analog die. The analog die temperature must not exceed 150C under these conditions Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 135C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SUPPLY VOLTAGE
Nominal Operating Voltage VSUP 8.0 - 18 V
SUPPLY CURRENT
NORMAL Mode VSUP = 12 V, Power Die ON (PSON = 1), MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled IRUN - 20 - mA
DIGITAL INTERFACE RATINGS (ANALOG DIE)
Output Terminals RST_A, IRQ_A Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Voltage (IOUT = 1.0 A) Output Terminals BEMF, RXD Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Voltage (IOUT = 1.5 mA) Output Terminal RXD - Capacitance (8) Input Terminals RST_A, FGEN, SS Input Logic Low Voltage Input Logic High Voltage Input Terminals RST_A, FGEN, SS - Capacitance (8) Terminals RST_A, IRQ_A - Pullup Resistor Terminal SS - Pullup Resistor Terminals FGEN, MOSI, SPSCK - Pulldown Resistor Terminal TXD - Pullup Current Source VIL VIH CIN RPULLUP1 RPULLUP2 RPULLDOWN IPULLUP - 3.5 - - - - - - - 4.0 10 60 60 35 1.5 - - - - - - pF k k k A VOL VOH CIN - 3.85 - - - 4.0 0.4 - - pF V VOL VOH - 3.85 - - 0.4 - V V
Notes 8. This parameter is guaranteed by process monitoring but is not production tested.
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 135C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SYSTEM RESETS AND INTERRUPTS
High-Voltage Reset Threshold Hysteresis Low-Voltage Reset Threshold Hysteresis High-Voltage Interrupt Threshold Hysteresis Low-Voltage Interrupt Threshold Hysteresis High-Temperature Reset (9) Threshold Hysteresis High-Temperature Interrupt (10) Threshold Hysteresis TION TIH - 5.0 160 - - - TRON TRH - 5.0 170 - - - VLVION VLVIH 6.5 - - 0.4 8.0 - VHVION VHVIH 17.5 - 21 1.0 23 - V VLVRON VLVRH 3.6 - 4.0 100 4.7 - V mV V VHVRON VHVRH 27 - 30 1.5 33 - V
C
C
VOLTAGE REGULATOR
Normal Mode Output Voltage IOUT = 60 mA, 6.0 V < VSUP < 18 V Load Regulation IOUT = 80 mA, VSUP = 9.0 V VLR - - 100 VDDRUN 4.75 5.0 5.25 mV V
Notes 9. This parameter is guaranteed by process monitoring but is not production tested. 10. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10C).
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 135C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN PHYSICAL LAYER
Output Low Level TXD LOW, 500 Pullup to VSUP Output High Level TXD HIGH, IOUT = 1.0 A Pullup Resistor to VSUP Leakage Current to GND Recessive State (- 0.5 V < VLIN < VSUP) Leakage Current to GND (VSUP Disconnected) Including Internal Pullup Resistor, VLIN @ -18 V Including Internal Pullup Resistor, VLIN @ +18 V LIN Receiver Recessive Dominant Threshold Input Hysteresis VIH VIL VITH VIHY 0.6 VLIN 0 - 0.01 VSUP - - VSUP / 2 - VSUP 0.4 VLIN - 0.1 VSUP IBUS_NO_GND IBUS - - - 600 25 - - V RSLAVE IBUS_PAS_REC 0.0 - 20 A VLIN-HIGH VSUP - 1.0 20 - 30 - 60 k A VLIN-LOW - - 1.4 V V
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STATIC ELECTRICAL CHARACTERISTICS
This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values
STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 135C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
HALF-BRIDGE OUTPUTS (HB1 : HB4)
Switch ON Resistance @ TJ = 25C with ILOAD = 1.0 A High Side Low Side High-Side Overcurrent Shutdown Low-Side Overcurrent Shutdown Low-Side Current Limitation @ TJ = 25C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) Half-Bridge Output HIGH Threshold for BEMF Detection Half-Bridge Output LOW Threshold for BEMF Detection Hysteresis for BEMF Detection Low-Side Current-to-Voltage Ratio (VADOUT [V] / IHB [A]) CSA = 1 CSA = 0 RATIOH RATIOL 7.0 1.0 12.0 2.0 14.0 3.0 RDS(ON)HB_HS RDS(ON)HB_LS - - 3.0 2.5 425 400 - - 500 500 7.5 7.5 m
IHBHSOC IHBLSOC
ICL1 ICL2 ICL3 ICL4 ICL5 VBEMFH VBEMFL VBEMFHY
A A
mA
- 210 300 450 600 - - -
55 260 370 550 740 - 30 - 60 30
- 315 440 650 880 0.0 - 5.0 - V mV mV V/A
SWITCHABLE VDD OUTPUT (HVDD)
Overcurrent Shutdown Threshold IHVDDOCT 24 30 40 mA
VSUP DOWN-SCALER
Voltage Ratio (RATIOVSUP = VSUP / VADOUT) RATIOVSUP 4.8 5.1 5.35 -
INTERNAL DIE TEMPERATURE SENSOR
Voltage / Temperature Slope Output Voltage @ 25C STTOV VT25 - 1.7 19 2.1 - 2.5 mV/ C V
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DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 135C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN PHYSICAL LAYER
Propagation Delay (11), (12) TXD LOW to LIN LOW TXD HIGH to LIN HIGH LIN LOW to RXD LOW LIN HIGH to RXD HIGH TXD Symmetry RXD Symmetry Output Falling Edge Slew Rate (11), (13) 80% to 20% Output Rising Edge Slew Rate (11), (13) 20% to 80%, RBUS > 1.0 k, CBUS < 10 nF LIN Rise / Fall Slew Rate Symmetry (11), (13) SRS SRR 1.0 - 2.0 2.0 - 3.0 2.0 s s t TXD-LIN-LOW t TXD-LIN-HIGH t LIN-RXD-LOW t LIN-RXD-HIGH t TXD-SYM t RXD-SYM SRF -1.0 - 2.0 - 3.0 V/s - - - - - 2.0 - 2.0 - - 4.0 4.0 - - 6.0 6.0 8.0 8.0 2.0 2.0 V/s
AUTONOMOUS WATCHDOG (AWD)
AWD Oscillator Period AWD Period Low = 512 t OSC AWD Period High = 256 t OSC t OSC t AWDPH t AWDPL - 16 8.0 40 22 11 - 28 14 s ms ms
Notes 11. All LIN characteristics are for initial LIN slew rate selection (20 kbaud) (SRS0 : SRS1= 00). 12. See Figure 4, page 12. 13. See Figure 5, page 12.
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MICROCONTROLLER PARAMETRICS
MICROCONTROLLER PARAMETRICS
MICROCONTROLLER For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Module Core Timer Flash RAM ADC SPI ESCI Description High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Two 16-Bit Timers with Two Channels (TIM A and TIM B) 16 K Bytes 512 Bytes 10-Bit Analog-to-Digital Converter SPI Module Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment Internal Clock Generation Module Special Counter for SMARTMOS BEMF Output
ICG BEMF Counter
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TIMING DIAGRAMS
TIMING DIAGRAMS
t TXD-LIN-LOW t
Tx-LIN-low
t TXD-LIN-HIGH tTx-LIN-high
TXD Tx TXD
LIN LIN
Recessive State
0.9 VSUP 0.9 VSUP
Recessive State
0.6 VSUP VSUP 0.4 VSUP VSUP 0.1 VSUP 0.1 VSUP
Dominant State
Rx RXD
t LIN-RXD-LOW t
LIN-Rx-low
t LIN-RXD-HIGH t
LIN-Rx-high
Figure 4. LIN Timing Description
t Fall-time
t Rise-time
0.8 VSUP 0.8 VSUP
0.8 VSUP VSUP
V Fall
V Rise
0.2 VSUP 0.2 VSUP
Dominant State
0.2 VSUP 0.2 VSUP
SRF =
V Fall t Fall-time
SRR =
V Rise t Rise-time
Figure 5. LIN Slew Rate Description
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TIMING DIAGRAMS
Functional Diagrams
1.6 1.4 1.2 1.0 TJ = 25C
Volts
Volts
0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Amperes Amperes H-Bridge Low Side
Figure 6. Free Wheel Diode Forward Voltage
250
200 TA = 125C
Dropout (mV) Drop Out (mV)
150
100
TA = 25C
50
TA = -40C
0 0 5 5.0 10
IILoad (mA) LOAD (mA)
15
20
25
Figure 7. Dropout Voltage on HVDD
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 908E626 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E626 is well suited to perform stepper motor control, e.g. for climate or light-levelling control via a 3-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS IC chip. The SMARTMOS IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS IC configured as four half-bridge outputs. Other ports are also provided including a selectable HVDD terminal. An internal voltage regulator is provided on the SMARTMOS IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and the third for ground.
FUNCTIONAL TERMINAL DESCRIPTION
See Figures 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on Figures 3 for a depiction of the terminal locations on the package.
PORT D I /O TERMINALS (PTD0:1)
PTD1/ TACH1 and PTD0/ TACH0/BEMF are specialfunction, bidirectional I /O port terminals that can also be programmed to be timer terminals. In step motor applications the PTD0 terminal should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 terminal is recommended for use as an output terminal for generating the FGEN signal (PWM signal) if required by the application.
PORT A I /O TERMINALS (PTA0:4)
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt terminals, KBD0 : KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet.
PORT E I /O TERMINAL (PTE1)
PTE1/ RXD and PTE0/ TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally.
PORT B I/O TERMINALS (PTB1, PTB3:7)
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6 : PTB7 terminals are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2 terminal is not accessible in this device. For details refer to the 68HC908EY16 datasheet.
EXTERNAL INTERRUPT TERMINAL (IRQ)
The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet.
PORT C I/O TERMINALS (PTC2:4)
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet.
EXTERNAL RESET TERMINAL (RST)
A logic [0] on the RST terminal forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet.
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FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION
CURRENT LIMITATION FREQUENCY INPUT TERMINAL (FGEN)
Input terminal for the half-bridge current limitation PWM frequency. This input is not a real PWM input terminal; it should just supply the period of the PWM. The duty cycle will be generated automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz.
systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs, multiple VSUP terminals are provided. All VSUP terminals must be connected to get full chip functionality.
POWER GROUND TERMINALS (GND1 AND GND2)
GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs multiple terminals are provided. GND1 and GND2 terminals must be connected to get full chip functionality.
BACK ELECTROMAGNETIC FORCE OUTPUT TERMINAL (BEMF)
This terminal gives the user information about back electromagnetic force (BEMF). This feature allows stall detection and coil failures in step motor applications. In order to evaluate this signal the terminal must be directly connected to terminal PTD0 / TACH0 / BEMF.
SWITCHABLE VDD OUTPUT TERMINAL (HVDD)
The HVDD terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; The output is short-circuit protected.
RESET TERMINAL (RST_A)
RST_A is the bidirectional reset terminal of the analog die.
It is an open drain with pullup resistor and must be connected to the RST terminal of the MCU.
+ 5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD)
The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. Important The VDD terminal should not be used to supply other loads; use the HVDD terminal for this purpose. The VDD, EVDD, VDDA, and VREFH terminals must be connected together.
INTERRUPT TERMINAL (IRQ_A)
IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. It is an open drain with pullup resistor and must be connected to the IRQ terminal of the MCU.
SLAVE SELECT TERMINAL (SS)
This terminal is the SPI Slave Select terminal for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I /O of the microcontroller.
VOLTAGE REGULATOR GROUND TERMINAL (VSS)
The VSS terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL terminals must be connected together.
LIN BUS TERMINAL (LIN)
The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification.
LIN TRANSCEIVER OUTPUT TERMINAL (RXD)
This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller's Enhanced Serial Communications Interface (ESCI) module (RXD terminal).
HALF-BRIDGE OUTPUT TERMINALS (HB1: HB4)
The 908E626 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1: HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. The HB1: HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low-side MOSFETs.
ADC REFERENCE TERMINALS (VREFL AND VREFH)
VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet.
POWER SUPPLY TERMINALS (VSUP1: VSUP3)
VSUP1: VSUP3 are device power supply terminals. The nominal input voltage is designed for operation from 12 V
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FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION
ADC SUPPLY TERMINALS (VDDA AND VSSA)
VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet.
Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet.
TEST TERMINAL (FLSVPP)
This terminal is for test purposes only. This terminal should be either left open (not connected) or connected to GND.
MCU POWER SUPPLY TERMINALS (EVDD AND EVSS)
EVDD and EVSS are the power supply and ground terminals. The MCU operates from a single power supply.
EXPOSED PAD TERMINAL
The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential.
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS INTERRUPTS
The 908E626 has five different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled.
INTERRUPT FLAG REGISTER (IFR)
Register Name and Address: IFR - $05 Bit 7 Read Write Reset
0 0
6
0 0
5
LINF 0
4
HTF 0
3
LVF 0
2
HVF 0
1
OCF
Bit 0
0
LOW-VOLTAGE INTERRUPT
The Low-Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low-voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high-side MOSFET only) are switched off. All other modules are not influenced by this interrupt.
0
0
LINF -- LIN FLAG BIT
This read / write flag is set on the falling edge at the LIN data line. Clear LINF by writing a logic [1] to LINF. Reset clears the LINF bit. Writing a logic [0] to LINF has no effect. * 1 = Falling edge on LIN data line has occurred. * 0 = Falling edge on LIN data line has not occurred since last clear.
HIGH-VOLTAGE INTERRUPT
The High-Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High-Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high-side MOSFET only) are switched off. All other modules are not influenced by this interrupt.
HTF -- HIGH-TEMPERATURE FLAG BIT
This read / write flag is set on a high-temperature condition. Clear HTF by writing a logic [1] to HTF. If a high-temperature condition is still present while writing a logic [1] to HTF, the writing has no effect. Therefore, a high-temperature interrupt cannot be lost due to inadvertent clearing of HTF. Reset clears the HTF bit. Writing a logic [0] to HTF has no effect. * 1 = High-temperature condition has occurred. * 0 = High-temperature condition has not occurred.
HIGH-TEMPERATURE INTERRUPT
The High-Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the HighTemperature Interrupt is enabled, an interrupt will be initiated.
LVF -- LOW-VOLTAGE FLAG BIT
This read / write flag is set on a low-voltage condition. Clear LVF by writing a logic [1] to LVF. If a low-voltage condition is still present while writing a logic [1] to LVF, the writing has no effect. Therefore, a low-voltage interrupt cannot be lost due to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a logic [0] to LVF has no effect. * 1 = Low-voltage condition has occurred. * 0 = Low-voltage condition has not occurred.
LIN INTERRUPT
If the LINIE bit is set, a falling edge on the LIN terminal will generate an interrupt.
OVERCURRENT INTERRUPT
If an overcurrent condition on a half-bridge or the HVDD output is detected and the OCIE bit is set and an interrupt generated.
HVF -- HIGH-VOLTAGE FLAG BIT
This read / write flag is set on a high-voltage condition. Clear HVF by writing a logic [1] to HVF. If high-voltage condition is still present while writing a logic [1] to HVF, the writing has no effect. Therefore, a high-voltage interrupt cannot be lost due to inadvertent clearing of HVF. Reset clears the HVF bit. Writing a logic [0] to HVF has no effect. * 1 = High-voltage condition has occurred. * 0 = High-voltage condition has not occurred.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
OCF -- OVERCURRENT FLAG BIT
This read-only flag is set on an overcurrent condition. Reset clears the OCF bit. To clear this flag, write a logic [1] to the appropriate overcurrent flag in the SYSSTAT Register. See Figure 8, which shows the two signals triggering the OCF. * 1 = High-current condition has occurred. * 0 = High-current condition has not occurred.
HVDD_OCF HB_OCF
HTIE -- HIGH-TEMPERATURE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the hightemperature flag, HTF. Reset clears the HTIE bit. * 1 = Interrupt requests from HTF flag enabled. * 0 = Interrupt requests from HTF flag disabled.
LVIE -- LOW-VOLTAGE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the lowvoltage flag, LVF. Reset clears the LVIE bit. * 1 = Interrupt requests from LVF flag enabled. * 0 = Interrupt requests from LVF flag disabled.
OCF
Figure 8. Principal Implementation for OCF
HVIE -- HIGH-VOLTAGE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the highvoltage flag, HVF. Reset clears the HVIE bit. * 1 = Interrupt requests from HVF flag enabled. * 0 = Interrupt requests from HVF flag disabled.
Bit 0
0
INTERRUPT MASK REGISTER (IMR)
Register Name and Address: IMR - $04 Bit 7 Read Write Reset
0 0
6
0 0
5
LINIE 0
4
HTIE 0
3
LVIE 0
2
HVIE 0
1
OCIE 0
0
OCIE -- Overcurrent Interrupt Enable Bit This read / write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit. * 1 = Interrupt requests from OCF flag enabled. * 0 = Interrupt requests from OCF flag disabled.
LINIE -- LIN LINE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the LIN flag, LINF. Reset clears the LINIE bit. * 1 = Interrupt requests from LINF flag enabled. * 0 = Interrupt requests from LINF flag disabled.
RESET
The 908E626 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. Figure 9 depicts the internal reset sources.
SPI REGISTERS
AWDRE Flag AWD Reset Sensor HVRE Flag High-Voltage Reset Sensor
VDD
HTRE Flag
RST_A
High-Temperature Reset Sensor
MONO FLOP Low-Voltage Reset
Figure 9. Internal Reset Routing
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RESET INTERNAL SOURCES
Autonomous Watchdog AWD modules generates a reset because of a timeout (watchdog function). High-Temperature Reset To prevent damage to the device, a reset will be initiated if the temperature rises above a certain value. The reset is maskable with bit HTRE in the Reset Mask Register. After a reset the high-temperature reset is disabled. Low-Voltage Reset The LVR is related to the internal VDD. In case the voltage falls below a certain threshold, it will pull down the RST_A terminal. High-Voltage Reset The HVR is related to the external VSUP voltage. In case the voltage is above a certain threshold, it will pull down the RST_A terminal. The reset is maskable with bit HVRE in the Reset Mask Register. After a reset the high-voltage reset is disabled.
Reset Mask Register (RMR)
Register Name and Address: RMR - $06 Bit 7 Read Write Reset
TTEST 0
6
0
5
0
4
0
3
0
2
0
1
HVRE 0
Bit 0
HTRE 0
0
0
0
0
0
TTEST -- High-Temperature Reset Test This read / write bit is for test purposes only. It decreases the overtemperature shutdown limit for final test. Reset clears the HTRE bit. * 1 = Low-temperature threshold enabled. * 0 = Low-temperature threshold disabled. HVRE -- High-Voltage Reset Enable Bit This read / write bit enables resets on high-voltage conditions. Reset clears the HVRE bit. * 1 = High-voltage reset enabled. * 0 = High-voltage reset disabled. HTRE -- High-Temperature Reset Enable Bit This read / write bit enables resets on high-temperature conditions. Reset clears the HTRE bit. * 1 = High-temperature reset enabled. * 0 = High-temperature reset disabled.
RESET EXTERNAL SOURCE
External Reset Terminal The microcontroller has the capability of resetting the SMARTMOS device by pulling down the RST terminal.
SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) creates the communication link between the microcontroller and the 908E626. The interface consists of four terminals (see Figure 10): * SS -- Slave Select * MOSI -- Master-Out Slave-In * MISO -- Master-In Slave-Out * SPSCK -- Serial Clock (maximum frequency 4.0 MHz) A complete data transfer via the SPI consists of 2 bytes. The master sends address and data, slave system status, and data of the selected address.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
SS
Read/Write, Address, Parity
Data (Register write) P X D7 D6 D5 D4 D3 D2 D1 D0
MOSI
R/W
A4
A3
A2
A1
A0
System Status Register
Data (Register read) S1 S0 D7 D6 D5 D4 D3 D2 D1 D0
MISO
S7
S6
S5
S4
S3
S2
SPSCK
Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data
Figure 10. SPI Protocol During the inactive phase of SS, the new data transfer is prepared. The falling edge on the SS line indicates the start of a new data transfer and puts MISO in the low-impedance mode. The first valid data are moved to MISO with the rising edge of SPSCK. The MISO output changes data on a rising edge of SPSCK. The MOSI input is sampled on a falling edge of SPSCK. The data transfer is only valid if exactly 16 sample clock edges are present in the active phase of SS. After a write operation, the transmitted data is latched into the register by the rising edge of SS. Register read data is internally latched into the SPI at the time when the parity bit is transferred. SS HIGH forces MISO to high impedance. * If R/ W = 1, the second byte of master contains no valid information, slave just transmits back register data. * If R/ W = 0, the master sends data to be written in the second byte, slave sends concurrently contents of selected register prior to write operation, write data is latched in the SMARTMOS register on rising edge of
SS.
Parity P The parity bit is equal to "0" if the number of 1 bits is an even number contained within R/ W, A4 : A0. If the number of 1 bits is odd, P equals "1". For example, if R/ W = 1, A4 : A0 = 00001, then P equals "0." The parity bit is only evaluated during a write operation. Bit X
MASTER ADDRESS BYTE
A4 : A0 Contains the address of the desired register.
Not used. Master Data Byte
R/W Contains information about a read or a write operation. Table 2. Contains data to be written or no valid data during a read operation.
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Table 3. List of Registers
Addr Register Name H-Bridge Output (HBOUT) H-Bridge Control (HBCTL) System Control (SYSCTL) Interrupt Mask (IMR) Interrupt Flag (IFR) Reset Mask (RMR) Analog Multiplexer Configuration (ADMUX) Reserved R/W R W R W R W R W R W R W R W R W $09 Reserved AWD Control (AWDCTL) Power Output (POUT) System Status (SYSSTAT) R W $0a R W R W R W 0 LINCL 0 0 0 0 0 AWDRST 0 AWDRE 0 0 AWDF AWDR 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 HB4_H 6 HB4_L 5 HB3_H 0 4 HB3_L 0 3 HB2_H 0 2 HB2_L 1 HB1_H 0 HB1_L
$01
$02
OFC_EN
CSA
CLS2 0
CLS1 0
CLS0
$03
PSON
SRS1
SRS0
0
0
0 0
$04
0
0
LINIE
HTIE
LVIE
HVIE
OCIE OCF
$05
0
0 0
LINF 0
HTF 0
LVF 0
HVF 0
0
$06
TTEST 0
HVRE
HTRE
$07
0
0
0
SS3 0
SS2
SS1
SS0
$08
0
0
0
$0b
0
0 LVF
0 HVF
HVDDON
0 HTF
$0c
HVDD_OCF
0
HB_OCF
Slave Status Byte Contains the contents of the System Status Register ($0c) independent of whether it is a write or read operation or which register was selected. Slave Data Byte Contains the contents of selected register. During a write operation it includes the register content prior to a write operation. SPI Register Overview Table 3 summarizes the SPI Register addresses and the bit names of each register.
ANALOG DIE I / OS
LIN Physical Layer The LIN bus terminal provides a physical layer for singlewire communication in automotive applications. The LIN
physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
TXD Terminal The TXD terminal is the MCU interface to control the state of the LIN transmitter (see Figure , page 2). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD terminal has an internal pullup current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. RXD Terminal The RXD transceiver terminal is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. Analog Multiplexer /ADOUT Terminal The ADOUT terminal is the analog output interface to the ADC of the MCU (see Figure , page 2). An analog multiplexer is used to read six internal diagnostic analog voltages. Current Recopy The analog multiplexer is connected to the four low-side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low-side MOSFET. High or low resolution is selectable: 5.0 V / 2.5 A or 5.0 V / 500 mA, respectively. (Refer to HalfBridge Current Recopy on page 25.) Temperature Sensor The 908E626 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. VSUP Prescaler The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP / RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. Analog Multiplexer Configuration Register (ADMUX)
Register Name and Address: ADMUX - $07 Bit 7 Read Write Reset
0 0 0 0 0
Table 4. Analog Multiplexer Configuration Register
SS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Not Used Channel Current Recopy HB1 Current Recopy HB2 Current Recopy HB3 Current Recopy HB4 VSUP Prescaler Temperature Sensor
Power Output Register (POUT)
Register Name and Address: POUT - $0b Bit 7 Read Write Reset
0 0 0
6
0
5
0
(14)
4
0
(14)
3
0
(14)
2
0
(14)
1
HVDDO N
Bit 0
0
(14)
0
0
0
0
0
0
Notes 14. This bit must always be set to 0.
HVDDON -- HVDD On Bit This read/write bit enables HVDD output. Reset clears the HVDDON bit. * 1 = HVDD enabled. * 0 = HVDD disabled.
6
0
5
0
4
0
3
SS3 0
2
SS2 0
1
SS1 0
Bit 0
SS0 0
HALF-BRIDGES
Outputs HB1 : HB4 provide four low-resistive half-bridge output stages. The half-bridges can be used in H-Bridge, high-side, or low-side configurations. Reset clears all bits in the H-Bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1: HB4 output features: * Short circuit (overcurrent) protection on high-side and low-side MOSFETs. * Current recopy feature (low side MOSFET).
SS3, SS2, SS1, and SS0 -- A / D Input Select Bits These read / write bits select the input to the ADC in the microcontroller according to Table 4, page 22. Reset clears SS3, SS2, SS1, and SS0 bits.
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* Overtemperature protection. * Overvoltage and undervoltage protection.
* Current limitation feature (low side MOSFET).
VSUP
On/Off Status
High-Side Driver
Charge Pump, Overtemperature Protection, Overcurrent Protection
Control
BEMF
HBx
On/Off Status Current Limit
Low-Side Driver
Current Recopy, Current Limitation, Overcurrent Protection
GND
Figure 11. Half-Bridge Push-Pull Output Driver Half-Bridge Control Each output MOSFET can be controlled individually. The general enable of the circuitry is done by setting PSON in the System Control Register (SYSCTL). HBx_L and HBx_H form one half-bridge. It is not possible to switch on both MOSFETs in one half-bridge at the same time. If both bits are set, the high-side MOSFET has a higher priority. To avoid both MOSFETs (high side and low side) of one half-bridge being on at the same time, a break-before-make circuit exists. Switching the high-side MOSFET on is inhibited as long as the potential between gate and VSS is not below a certain threshold. Switching the low-side MOSFET on is blocked as long as the potential between gate and source of the high-side MOSFET did not fall below a certain threshold. Half-Bridge Output Register (HBOUT)
Register Name and Address: HBOUT - $01 Bit 7 Read Write Reset
HB4_ H 0
6
HB4_ L 0
5
HB3_ H 0
4
HB3_ L 0
3
HB2_ H 0
2
HB2_ L 0
1
HB1_ H 0
Bit 0
HB1_ L 0
HBx_L -- Low-Side On / Off Bits These read / write bits turn on the low-side MOSFETs. Reset clears the HBx_L bits. * 1 = Low-side MOSFET turned on for half-bridge output x. * 0 = Low-side MOSFET turned off for half-bridge output x. HBx_H -- High-Side On/Off Bits These read / write bits turn on the high-side MOSFETs. Reset clears the HBx_H bits. * 1 = High-side MOSFET turned on for half-bridge output x.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
* 0 = High-side MOSFET turned on for half-bridge output x.
The recommended frequency range for the FGEN and the PWM is 0.1 kHz to 20 kHz. Functionality Each low-side MOSFET switches off if a current above the selected current limit was detected. The 908E626 offers five different current limits (refer to Table 5, page 27, for current limit values). The low-side MOSFET switches on again if a rising edge on the FGEN input was detected (Figure 12).
HALF-BRIDGE CURRENT LIMITATION
Each low-side MOSFET offers a current limit or constant current feature. This features is realized by a pulse width modulation on the low-side MOSFET. The pulse width modulation on the outputs is controlled by the FGEN input and the load characteristics. The FGEN input provides the PWM frequency, whereas the duty cycle is controlled by the load characteristics.
Coil Current
H-Bridge low-side MOSFET will be switched off if select current limit is reached.
H-Bridge low-side MOSFET will be turned on with each rising edge of the FGEN input. t (s) Half-Bridge Low-Side Output
t (s) FGEN Input (MCU PWM Signal)
t (s) Minimum 50 s
Figure 12. Half-Bridge Current Limitation Offset Chopping If bit OFC_EN in the H-Bridge Control Register (HBCTL) is set, HB1 and HB2 will continue to switch on the low-side MOSFETs with the rising edge of the FGEN signal and HB3 and HB4 will switch on the low-side MOSFETs with the falling edge on the FGEN input. In step motor applications, this
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feature allows the reduction of EMI due to a reduction of the di/dt (Figure ).
Coil1 Current
Coil2 Current
FGEN Input (MCU PWM Signal)
HB1 HB2 HB3 HB4
Coil1.....
Coil2.....
Current in VSUP Line
Figure 13. Offset Chopping for Step Motor Control
HALF-BRIDGE CURRENT RECOPY
Each low-side MOSFET has an additional sense output to allow a current recopy feature. This sense source is internally connected to a shunt resistor. The drop voltage is amplified and switched to the analog multiplexer. The factor for the current sense amplification can be selected via bit CSA in the System Control Register. * CSA = 1: Low resolution selected (500 mA measurement range). * CSA = 0: High resolution selected (2.5 A measurement range).
HALF-BRIDGE BEMF GENERATION
The BEMF output is set to "1" if a recirculation current is detected in any half-bridge. This recirculation current flows via the two freewheeling diodes of the power MOSFETs. The BEMF circuitry detects that and generates a HIGH on the BEMF output as long as a recirculation current is detected. This signal provides a flexible and reliable detection of stall in step motor applications. For this the BEMF circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. In addition the signal can be used for open load detection (absence of this signal) (see Figure 14, page 26).
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Coil Current
Voltage on 1
1
BEMF Signal
Figure 14. BEMF Signal Generation
HALF-BRIDGE OVERTEMPERATURE PROTECTION
The half-bridge outputs provide an overtemperature prewarning with the HTF in the Interrupt Flag Register (IFR). In order to protect the outputs against overtemperature, the High-Temperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs.
done by the low- and high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the outputs are automatically disabled. The overvoltage / undervoltage status flags are cleared (and the outputs re-enabled) by writing a logic [1] to the LVF / HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present. Half-Bridge Control Register (HBCTL)
Register Name and Address: HBCTL - $02 Bit 7 Read Write Reset
OFC_EN 0
HALF-BRIDGE OVERCURRENT PROTECTION
The half-bridges are protected against short to GND, short to VSUP, and load shorts. In the event an overcurrent on the high side is detected, the high-side MOSFETs on all HB high-side MOSFETs are switched off automatically. In the event an overcurrent on the low side is detected, all HB low-side MOSFETs are switched off automatically. In both cases, the overcurrent status flag HB_OCF in the System Status Register (SYSSTAT) is set. The overcurrent status flag is cleared (and the outputs reenabled) by writing a logic [1] to the HB_OCF flag in the System Status Register or by reset.
6
CSA 0
5
0
4
0
3
0
2
CLS2
1
CLS1 0
Bit 0
CLS0 0
0
0
0
0
OFC_EN -- H-Bridge Offset Chopping Enable Bit This read / write bit enables offset chopping. Reset clears the OFC_EN bit. * 1 = Offset chopping enabled. * 0 = Offset chopping disabled.
HALF-BRIDGE OVERVOLTAGE / UNDERVOLTAGE
The half-bridge outputs are protected against undervoltage and overvoltage conditions. This protection is
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CSA -- H-Bridges Current Sense Amplification Select Bit This read / write bit selects the current sense amplification of the H-Bridges. Reset clears the CSA bit. * 1 = Current sense amplification set for measuring 0.5 A. * 0 = Current sense amplification set for measuring 2.5 A. CLS2 : CLS0 -- H-Bridge Current Limitation Selection Bits These read / write bits select the current limitation value according to Table 5. Reset clears the CLS2 : CLS0 bits. Table 5. H-Bridge Current Limitation Value Selection
CLS2 0 0 0 0 1 1 1 1 CLS1 0 0 1 1 0 0 1 1 CLS0 0 1 0 1 0 1 0 1 55 mA (typ) 260 mA (typ) 370 mA (typ) 550 mA (typ) 740 mA (typ) No Limit Current Limit
System Control Register (SYSCTL)
Register Name and Address: SYSCTL - $03 Bit 7 Read Write Reset
PSON 0
6
SRS1 0
5
SRS0 0
4
0
3
0
2
0
1
0
Bit 0
0
(14)
0
0
0
0
0
Notes 15. This bit must always be set to 0.
PSON -- Power Stages On Bit This read / write bit enables the power stages (half-bridges, LIN transmitter and HVDD output). Reset clears the PSON bit. * 1 = Power stages enabled. * 0 = Power stages disabled. SRS0 : SRS1 -- LIN Slew Rate Selection Bits These read / write bits enable the user to select the appropriate LIN slew rate for different baud rate configurations as shown in Table 6. The high speed slew rates are used, for example, for programming via the LIN and are not intended for use in the application. Table 6. LIN Slew Rate Selection Bits
SRS1 0 0 1 1 SRS0 0 1 0 1 LIN Slew Rate Initial Slew Rate (20 kBaud) Slow Slew Rate (10 kBaud) High Speed II (8 x) High Speed I (4 x)
Bits
Switchable VDD Outputs
The HVDD terminal is a switchable VDD output terminal. It can be used for driving external circuitry that requires a VDD voltage. The output is enabled with bit PSON in the System Control Register and can be switched on / off with bit HVDDON in the Power Output Register. Low- or high-voltage conditions (LVI / HVI) have no influence on this circuitry.
HVDD Overtemperature Protection
Overtemperature protection is enabled if the hightemperature reset is enabled.
System Status Register (SYSSTAT)
Register Name and Address: SYSSTAT - $0c Bit 7 Read Write Reset
0 0 0
HVDD Overcurrent Protection
The HVDD output is protected against overcurrent. In the event the overcurrent limit is or was reached, the output automatically switches off and the HVDD overcurrent flag in the System Status Register is set.
6
LINCL
5
HVDD _OCF 0
4
0 0
3
LVF
2
HVF
1
HB_ OCF 0
Bit 0
HTF
0
0
0
LINCL -- LIN Current Limitation Bit This read-only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation in the transmitter, software is advised to turn the transmitter off immediately. * 1 = Transmitter operating in current limitation region. * 0 = Transmitter not operating in current limitation region.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
HVDD_OCF -- HVDD Output Overcurrent Flag Bit This read / write flag is set on an overcurrent condition at the HVDD terminal. Clear HVDD_OCF and enable the output by writing a logic [1] to the HVDD_OCF Flag. Reset clears the HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect. * 1 = Overcurrent condition on HVDD has occurred. * 0 = No overcurrent condition on HVDD has occurred. LVF -- Low-Voltage Bit This read only bit is a copy of the LVF bit in the Interrupt Flag Register. * 1 = Low-voltage condition has occurred. * 0 = No low-voltage condition has occurred. HVF -- High-Voltage Sensor Bit This read-only bit is a copy of the HVF bit in the Interrupt Flag Register. * 1 = High-voltage condition has occurred. * 0 = No high-voltage condition has occurred. HB_OCF -- H-Bridge Overcurrent Flag Bit This read / write flag is set on an overcurrent condition at the H-Bridges. Clear HB_OCF and enable the H-Bridge driver by writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a logic [0] to HB_OCF has no effect. * 1 = Overcurrent condition on H-Bridges has occurred. * 0 = No overcurrent condition on H-Bridges has occurred. HTF -- Overtemperature Status Bit This read-only bit is a copy of the HTF bit in the Interrupt Flag Register. * 1 = Overtemperature condition has occurred. * 0 = No overtemperature condition has occurred.
If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. Autonomous Watchdog Control Register (AWDCTL)
Register Name and Address: AWDCTL - $0a Bit 7 Read Write Reset
0 0 0
6
0
5
0
AWDRST
4
AWDRE
3
0
(14)
2
0
(14)
1
0 0
Bit 0
AWDR
0
0
0
0
0
Notes 16. This bit must always be set to 0.
AWDRST -- Autonomous Watchdog Reset Bit This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit. * 1 = Reset AWD and restart timeout period. * 0 = No effect. AWDRE -- Autonomous Watchdog Reset Enable Bit This read / write bit enables resets on AWD time-outs. A reset on the RST_A is asserted when the Autonomous Watchdog has reached the timeout and the Autonomous Watchdog is enabled. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit. * 1 = Autonomous watchdog enabled. * 0 = Autonomous watchdog disabled. AWDR -- Autonomous Watchdog Rate Bit This read / write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit. * 1 = Fast rate selected (10 ms). * 0 = Slow rate selected (20 ms).
AUTONOMOUS WATCHDOG (AWD)
The Autonomous Watchdog module allows to protect the CPU against code runaways. The AWD is enabled if AWDRE in the AWDCTL Register is set. If this bit is cleared, the AWD oscillator is disabled and the watchdog switched off. Watchdog The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software.
VOLTAGE REGULATOR
The 908E626 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the MCU. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E626, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the empty (0xFF) state: * 0xFD80: 0xFDDF Trim and Calibration Values * 0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values Below the usage of the trim values located in the flash memory is explained Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as 25 percent due to process, temperature, and voltage dependencies. To compensate this dependancies a ICG trim values is located at adress $FDC2. After trimming the ICG is a range of typ. 2% (3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) VDD = 5V, TAmbient~25C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at adress $38 of the MCU. Important The value has to be copied after every reset.
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TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION
TYPICAL APPLICATIONS
DEVELOPMENT SUPPORT
As the 908E626 has the MC68HC908EY16 MCU embedded typically all the development tools available for the MCU also apply for this device, however due to the fact of the additional analog die circuitry and the nominal +12V supply voltage some additional items have to be considered: * nominal 12V rather than 5V or 3V supply * high voltage VTST might be applied not only to IRQ terminal, but IRQ_A terminal For a detailed information on the MCU related development support see the MC68HC908EY16 datasheet section development support. The programming is principially possible at two stages in the manufacturing process - first on chip level, before the IC is soldered onto a pcb board and second after the IC is soldered onto the pcb board. Chip level programming On Chip level the easiest way is to only power the MCU with +5V (see Figure 15) and not to provide the analog chip with VSUP, in this setup all the analog terminal should be left open (e.g. VSUP[1:3]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well descripted in the MC68HC908EY16 datasheet - section development support.
VSUP[1:3] GND[1:2]
VDD VSS +5V VREFH VDDA
RST EVDD RST_A +5V 1 1F + 3 4 1F + 5 C2C1C2+ GND V+ 15 2 6 1F 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 5 R2OUT 9 2 1 3 6 4 5 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK +5V + CLK PTC4/OSC1 PTB4/AD4 10k 10k +5V C1+ VCC 16 + 1F 1F VTST IRQ IRQ_A VREFL 100nF 4.7F
MM908E626
VSSA EVSS
MAX232
V-
RS232 DB-9
2
Figure 15. Normal Monitor Mode Circuit (MCU only) Of course its also possible to supply the whole system with Vsup (12V) instead as descibted in Figure 16, page 31. PCB level programming If the IC is soldered onto the pcb board its typically not possible to seperately power the MCU with +5V, the whole
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION
system has to be powered up providing VSUP (see Figure 16).
VDD VSUP 47F + 100nF VSUP[1:3] GND[1:2] VDD VSS VREFH VDDA RST EVDD RST_A VDD 1 1F + 3 4 1F + 5 C2C1C2+ GND V+ 15 2 6 1F 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 5 R2OUT 9 2 1 3 6 4 5 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK VDD + CLK PTC4/OSC1 PTB4/AD4 10k 10k VDD C1+ VCC 16 + 1F 1F VTST IRQ IRQ_A VREFL 100nF 4.7F
MM908E626
VSSA EVSS
MAX232
V-
RS232 DB-9
2
Figure 16. Normal Monitor Mode Circuit Table 7 summarizes the possible configurations and the necessary setups. Table 7. Monitor Mode Signal Requirements and Options
Reset Vector Serial Communication
PTA0 Normal Monitor
Mode
IRQ RST
Mode Selection PTB3
0
ICG
COP
PTA1
0
PTB4
1 OFF OFF disabled disabled disabled
Communication Speed Normal Request Baud Bus Timeout External Clock Frequency Rate
disabled disabled disabled 9.8304 MHz 9.8304 MHz -- 2.4576 MHz 2.4576 MHz Nominal 1.6MHz Nominal 1.6MHz 9600 9600 Nominal 6300 Nominal 6300
VTST VDD
VDD
X
1
Forced Monitor
VDD GND
$FFFF (blank)
1
0
X
X ON
User
VDD
VDD
not $FFFF (not blank)
X
X
X
X
ON
enabled
enabled
--
Notes 1. PTA0 must have a pullup resistor to VDD in monitor mode 2. 3. 4. 5. External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don't care VTST is a high voltage VDD + 3.5V VTST VDD + 4.5V
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION
EMC/EMI RECOMMENDATIONS
This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale website www.freescale.com. VSUP terminals (VSUP1:VSUP3) Its recommended to place a high-quality ceramic decoupling capacitor close to the VSUP terminals to improve EMC/EMI behaviour. LIN terminal For DPI (Direct Power Injection) and ESD (Electro Static Discharge) its recommended to place a high-quality ceramic decoupling capacitor near the LIN terminal. An additional varistor will further increase the immunity against ESD. A ferrit in the LIN line will suppress some of the noise induced. Voltage regulator output terminals (VDD and AGND) Use a high-quality ceramic decoupling capacitor to stabilize the regulated voltage.
D1 VSUP C1 + C2 VSUP1 VSUP2 VSUP3 VREFH L1 LIN V1 C5 C3 C4 EVSS VSSA VREFL GND2 LIN EVDD VDDA VDD VSS
MCU digital supply terminals (EVDD and EVSS) Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. MCU analog supply terminals (VREFH, VDDA and VREFL, VSSA) To avoid noise on the analog supply terminals its important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via seperate traces and connected to the voltage regulator output. Figure 17 and Figure 18 show the recommendations on schematics and layout level and Table 8 incidates recommended external components and layout considerations.
MM908E625
GND1
Figure 17. EMC/EMI recommendations
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VDD NC VREFH VDDA EVDD EVSS VSSA VREFL
54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS 40 39 38 37 36 LIN NC NC VSUP1 GND1 VSUP2 NC VSUP3 GND2 35 34 33 32 31 30 29 28
908E626
C3 C4
C5
LIN
L1 V1
20 21 22 23 24 25 26 27
GND C1
C2
VBAT
Figure 18. PCB Layout Recommendations . Table 8. Component Value Recommendation
Component C1 C2 C3 Recommended Value(1) Bulk Capacitor 100nF, SMD Ceramic, Low ESR 100nF, SMD Ceramic, Low ESR Close (<5mm) to VSUP1, VSUP2 terminals with good ground return Close (<3mm) to digital supply terminals (EVDD, EVSS) with good ground return. The positive analog (VREFH, VDDA) and the digital (EVDD) supply should be connected right at the C3. C4 C5 4,7uF, SMD Ceramic, Low ESR 180pF, SMD Ceramic, Low ESR Bulk Capacitor Close (<5mm) to LIN terminal. Total Capacitance on LIN has to be below 220pF. (Ctotal = CLIN-Terminal + C5 + CVaristor ~ 10pF + 180pF + 15pF) V1(2) L1
(2)
Comments / Signal routing
Varistor Type TDK AVR-M1608C270MBAAB SMD Ferrite Bead Type TDK MMZ2012Y202B
Optional (close to LIN connector) Optional, (close to LIN connector)
Notes 1. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer's responsibility to validate their application. 2. Components are recommended to improve EMC and ESD performance.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS PACKAGING DIMENSIONS
PACKAGING DIMENSIONS
Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL105910.
10.3 5 7.6 7.4 C 9 B 2.65 2.35
52X 54
1
0.65
PIN 1 INDEX
4 9 B B 18.0 17.8 C L
27
28
5.15
2X 27 TIPS
A
54X
SEATING PLANE
0.3
ABC
0.10 A
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF HTE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTOM OF THE PLASTIC BODY.
A R0.08 MIN C A 8 0 0.9 0.5 0.1 0.0 SECTION B-B C 0.25
GAUGE PLANE
0MIN
(1.43)
10.9 9.7 0.30 A B C
(0.29) 0.30 0.25 0.38 0.22 0.13
M
BASE METAL
5.3 4.8 0.30 A B C DWB SUFFIX 54-TERMINAL PLASTIC PACKAGE 98Axxxxxxxx ISSUE B VIEW C-C
(0.25)
6
PLATING
A BC
8
SECTION A-A
ROTATED 90 CLOCKWISE
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Analog Integrated Circuit Device Data Freescale Semiconductor
ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Introduction This thermal addendum ia provided as a supplement to the MM908E626 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application and packaging information is provided in the data sheet. Package and Thermal Considerations This MM908E626 is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2
=
908E626
54-TERMINAL SOICW-EP
DWB SUFFIX 98ARL105910 54-TERMINAL SOICW-EP Note For package dimensions, refer to the 908E626 device datasheet.
RJA11 RJA12 RJA21 RJA22
.
P1 P2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 9. Thermal Performance Comparison
Thermal Resistance RJAmn (1)(2) RJBmn RJAmn
(2)(3) (1)(4)
1 = Power Chip, 2 = Logic Chip [C/W] m = 1, n=1 23 9.0 52 1.0 m = 1, n = 2 m = 2, n = 1 20 6.0 47 0 m = 2, n=2 24 10 52 2.0
1.0 1.0 0.2 0.2 * All measurements are in millimeters Soldermast openings Thermal vias connected to top buried plane
RJCmn (5)
Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad.
54 Terminal SOIC-EP 0.65 mm Pitch 17.9 mm x 7.5 mm Body 10.3 mm x 5.1 mm Exposed Pad Figure 19. Thermal Land Pattern for Direct Thermal Attachment Per JEDEC JESD51-5Thermal Test Board
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3
IRQ RST
PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF
RST_A IRQ_A SS
LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Exposed Pad
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS NC VDD NC NC NC HVDD NC HB4 VSUP3 GND2 HB3 NC
A
908E626 Terminal Connections
54-Terminal SOICW-EP 0.65 mm Pitch 17.9 mm x 7.5 mm Body 10.3 mm x 5.1 mm Exposed Pad
Figure 20. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 10. Thermal Resistance Performance
Thermal Resistance
Area A (mm2)
0 300 600
1 = Power Chip, 2 = Logic Chip (C/W) m = 1, n=1 53 39 35 21 15 14 m = 1, n = 2 m = 2, n = 1 48 34 30 16 11 9.0 m = 2, n=2 53 38 34 20 15 13
Outline:
RJAmn
Area A: Ambient Conditions:
RJSmn
0 300 600
RJA is the thermal resistance between die junction and ambient air. RJSmn is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
60
Thermal Resistance [C/W]
50 40 30 20 10 0
x
RJA11 RJA22 RJA12 = RJA21
0
300
Heat spreading area A [mm]
600
Figure 21. Device on Thermal Test Board RJA
100
Thermal Resistance [C/W]
10
1
x
0.1 1.00E-03
RJA11 RJA22 RJA12 = RJA21
1.00E-02
1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 22. Transient Thermal Resistance RJA (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2)
908E626
Analog Integrated Circuit Device Data Freescale Semiconductor
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How to Reach Us:
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MM908E626 Rev 3.0 12/2005

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